CPU Architecture

Overview

The Central Processing Unit (CPU) is the brain of a computer system. It fetches instructions from memory, decodes them, executes them, and writes back results. Understanding CPU architecture is fundamental to systems programming, performance optimization, and answering placement interview questions.

This section covers the foundational models (Von Neumann and Harvard), instruction set architectures, the CISC vs RISC debate, and the internal components—registers, ALU, control unit, and microcode—that make a CPU work.

CPU Block Diagram

graph TB
    subgraph "CPU Core"
        subgraph "Frontend"
            FETCH[Fetch Unit]
            DECODE[Decode Unit]
            RENAME[Register Rename]
        end
        subgraph "Backend"
            ISSUE[Issue/Dispatch]
            subgraph "Execution Units"
                ALU0[ALU 0]
                ALU1[ALU 1]
                FPU[FPU]
                LSU[Load/Store Unit]
                BRU[Branch Unit]
            end
            ROB[Reorder Buffer]
            RET[Retire Unit]
        end
        subgraph "Registers"
            ARF[Architectural Register File]
            PRF[Physical Register File]
        end
        subgraph "Cache"
            IL1[I-L1 Cache]
            DL1[D-L1 Cache]
            TLB[TLB]
        end
    end
    L2[L2 Cache] --> DL1
    L2 --> IL1
    MEM[Main Memory] --> L2

    FETCH -->|Instruction Bytes| DECODE
    DECODE -->|Micro-ops| RENAME
    RENAME --> ISSUE
    ISSUE --> ALU0
    ISSUE --> ALU1
    ISSUE --> FPU
    ISSUE --> LSU
    ISSUE --> BRU
    ALU0 --> ROB
    ALU1 --> ROB
    FPU --> ROB
    LSU --> ROB
    BRU --> ROB
    ROB --> RET
    FETCH -->|Request| IL1
    LSU -->|Data Request| DL1
    FETCH -->|Virtual Address| TLB

Core CPU Components

1. Control Unit (CU)

The control unit is the orchestrator of the CPU. It directs the operation of all other components.

Hardwired vs Microprogrammed Control:

2. Arithmetic Logic Unit (ALU)

The ALU performs all arithmetic and logical operations.

┌─────────────────────────────────┐
│              ALU                │
│  ┌─────────┐  ┌─────────────┐  │
│  │ Adder   │  │ Logic Unit  │  │
│  │(Add/Sub)│  │(AND/OR/XOR) │  │
│  └─────────┘  └─────────────┘  │
│  ┌─────────┐  ┌─────────────┐  │
│  │ Shifter │  │ Comparator  │  │
│  │(<<>>)  │  │ (< > =)     │  │
│  └─────────┘  └─────────────┘  │
│                                 │
│  Inputs: A, B, ALUControl      │
│  Outputs: Result, Flags (Z,C,N,V)│
└─────────────────────────────────┘

ALU Operations:

3. Registers

Registers are the fastest storage in the CPU, accessed in a single clock cycle.

Register Categories

Register Count Comparison

4. Fetch-Decode-Execute Cycle

The fundamental cycle of CPU operation:

graph LR
    F[Fetch] --> D[Decode]
    D --> E[Execute]
    E --> M[Memory Access]
    M --> W[Write Back]
    W --> F

Detailed steps:

5. Addressing Modes

How instructions specify operand locations:

CPU Performance Factors

What Makes a CPU Fast?

CPU Performance = f(Pipeline Depth, Width, Cache, Branch Prediction, OoO)

Pipeline Depth:    Deeper = higher clock rate, but higher branch mispredict penalty
Superscalar Width: Wider = more IPC, but harder to keep fed
Cache Hierarchy:   Larger/faster caches = fewer memory stalls
Branch Prediction: Better prediction = fewer pipeline flushes
Out-of-Order:      More reorder capacity = better ILP extraction

Pipeline Depth Tradeoff

Interview Focus

• Explain the Von Neumann bottleneck and how Harvard architecture addresses it
• Compare CISC and RISC with real-world examples (x86 vs ARM)
• Describe the fetch-decode-execute cycle step by step
• Explain why registers are the fastest storage and how many a typical CPU has
• Differentiate between the ISA (what the CPU can do) and microarchitecture (how it does it)
• Describe the role of the ALU, control unit, and register file
• Explain how addressing modes affect instruction encoding and flexibility

Cross References

• Von Neumann Architecture
• Harvard Architecture
• ISA
• CISC vs RISC
• Registers
• ALU
• Control Unit
• Microcode
• Pipelining