x86-64 Architecture

Overview

x86-64 (also called AMD64 or Intel 64) is the 64-bit extension of the x86 ISA. Originally developed by AMD (AMD64, 2003) and adopted by Intel (EM64T/Intel 64), it’s the dominant architecture for desktops, laptops, and servers. x86-64 is a CISC (Complex Instruction Set Computer) architecture with variable-length instructions.

x86-64 Key Features

Register Extension

graph TD
    subgraph "x86 (32-bit)"
        EAX["EAX (32-bit)"]
        EBX["EBX"]
        ECX["ECX"]
        EDX["EDX"]
        ESI["ESI"]
        EDI["EDI"]
        EBP["EBP"]
        ESP["ESP"]
    end
    subgraph "x86-64 (64-bit)"
        RAX["RAX (64-bit)"]
        RBX["RBX"]
        RCX["RCX"]
        RDX["RDX"]
        RSI["RSI"]
        RDI["RDI"]
        RBP["RBP"]
        RSP["RSP"]
        R8["R8"]
        R9["R9"]
        R15["...R15"]
    end

Calling Convention (System V AMD64)

Arguments passed in registers (not on stack):

Integer args: RDI, RSI, RDX, RCX, R8, R9
Float args:   XMM0-XMM7
Return:       RAX (integer), XMM0 (float)
Callee-saved: RBX, RBP, R12-R15

Instruction Encoding

x86-64 uses variable-length instructions (1-15 bytes):

┌──────────┬──────────┬──────────┬──────────┬──────────┐
│ Prefixes │  REX     │ Opcode   │ ModR/M   │ SIB      │
│ (0-4B)   │ (0-1B)   │ (1-3B)   │ (0-1B)   │ (0-1B)   │
├──────────┼──────────┼──────────┼──────────┼──────────┤
│ Displacement │ Immediate │
│ (0-4B)       │ (0-8B)    │
└──────────────┴───────────┘

• REX prefix: 64-bit operand size, extended registers (R8-R15)
• ModR/M: Addressing mode and register operands
• SIB: Scale-Index-Base addressing

x86-64 vs ARM vs RISC-V

Out-of-Order Execution

Modern x86-64 processors use aggressive out-of-order execution:

flowchart TD
    Fetch["Fetch"] --> Decode["Decode (CISC → μops)"]
    Decode --> Rename["Register Rename"]
    Rename --> Dispatch["Dispatch to Reservation Stations"]
    Dispatch --> Execute["Out-of-Order Execute"]
    Execute --> Retire["Retire (In-Order)"]

Micro-ops (μops)

Complex x86 instructions are decoded into simpler micro-ops:

ADD [RAX], RBX  →  μop1: LOAD tmp, [RAX]
                    μop2: ADD tmp, RBX
                    μop3: STORE [RAX], tmp

This allows CISC instructions to be executed on RISC-like backends.

Branch Prediction

Modern x86-64 has sophisticated branch prediction:

Misprediction penalty: 15-20 cycles on modern CPUs.

Memory Model (TSO)

x86-64 uses Total Store Order (TSO):

• Stores may be buffered (store buffer)
• Loads may bypass stores to different addresses
• All stores become visible in FIFO order
• Strongest memory model among mainstream ISAs

// x86-64: This works without barriers
*data = 42;
*flag = 1;  // Other cores see data=42 before flag=1

// ARM/RISC-V: Need explicit barrier
*data = 42;
__asm__ __volatile__("dmb sy" ::: "memory");
*flag = 1;

x86-64 Extensions Timeline

Interview Questions

1. Q: What are the key differences between x86-64 and x86 (32-bit)? A: x86-64 adds: 16 general-purpose registers (vs 8), 64-bit register width, 16 SIMD registers, register-based calling convention, 64-bit address space. Instructions use REX prefix for 64-bit operations and extended registers (R8-R15).

2. Q: Why is x86-64 considered CISC but executes like RISC? A: x86-64 has complex, variable-length instructions (CISC). But internally, the decoder breaks them into simple micro-ops (μops) that execute on a RISC-like backend. This gives CISC compatibility with RISC execution efficiency.

3. Q: What is TSO and why does it matter? A: Total Store Order is x86-64’s memory model. Stores may be buffered but become visible in order. Loads may bypass stores to different addresses. TSO is the strongest mainstream memory model, meaning fewer explicit barriers are needed compared to ARM/RISC-V.

4. Q: How does x86-64’s variable-length instruction encoding affect performance? A: Variable-length instructions make decoding complex (must determine instruction boundaries). Modern CPUs use a pre-decoder and micro-op cache to mitigate this. Fixed-length ISAs (ARM, RISC-V) have simpler decoding but may use more instructions.

5. Q: What is the significance of the register-based calling convention in x86-64? A: x86 (32-bit) passes arguments on the stack (slow, memory accesses). x86-64 passes the first 6 integer and 8 float arguments in registers (fast, no memory). This significantly reduces function call overhead.

Common Mistakes

• ❌ Confusing x86-64 with x86 (different register counts, calling conventions)
• ❌ Not knowing that x86-64 instructions are decoded into micro-ops
• ❌ Forgetting that TSO is a strong memory model (fewer barriers needed)
• ❌ Assuming variable-length instructions are always slower
• ❌ Not knowing about the 16 GPRs in x86-64

Summary

x86-64 extends x86 to 64 bits with 16 GPRs, register-based calling, and larger address space. It’s CISC externally but executes micro-ops on a RISC-like backend. TSO provides a strong memory model. Modern extensions (AVX, AVX-512, AMX) add SIMD and matrix operations for AI.

Cross-References

• ARM — RISC alternative
• RISC-V — Open-source RISC
• Alder Lake — Intel hybrid design
• AMD Zen — AMD’s implementation
• AVX — x86-64 SIMD

Cross References

• CISC vs RISC
• ISA
• Alder Lake
• AMD Zen