CPU Performance Equation

Overview

The CPU performance equation breaks down execution time into three fundamental components: instruction count, cycles per instruction (CPI), and clock period. This decomposition is essential for understanding where performance bottlenecks lie and how to optimize them.

The Fundamental Equation

CPU Time = Instruction Count × CPI × Clock Period

Or equivalently:

CPU Time = Instruction Count × CPI / Clock Rate

Components

Breaking Down the Equation

Instruction Count (IC)

The number of instructions executed:

• Reduced by: Better algorithms, compiler optimization, ISA choice (CISC vs RISC)
• Example: A RISC processor may execute more instructions than CISC for the same task

CPI (Cycles Per Instruction)

Average cycles per instruction:

CPI = Σ (CPI_i × Fraction_i)

Where CPI_i is the CPI for instruction type i,
and Fraction_i is the fraction of instructions of type i.

Example:

Clock Period / Clock Rate

Clock Period = 1 / Clock Rate

3 GHz processor: Clock Period = 1 / 3×10⁹ = 0.333 ns
5 GHz processor: Clock Period = 1 / 5×10⁹ = 0.200 ns

Performance Optimization Strategies

graph TD
    A["CPU Time = IC × CPI × T"] --> B["Reduce IC"]
    A --> C["Reduce CPI"]
    A --> D["Reduce T (increase clock rate)"]
    B --> B1["Better algorithms"]
    B --> B2["Compiler optimization"]
    B --> B3["ISA choice (CISC vs RISC)"]
    C --> C1["Better pipeline"]
    C --> C2["Cache optimization"]
    C --> C3["Branch prediction"]
    C --> C4["Out-of-order execution"]
    D --> D1["Smaller transistors"]
    D --> D2["Better voltage/frequency"]

Detailed Example

Scenario: Comparing Two Processors

Processor A: 2 GHz, CPI = 1.2 Processor B: 3 GHz, CPI = 2.0

Both run the same program with 1 billion instructions.

Time_A = IC × CPI_A / f_A = 10⁹ × 1.2 / 2×10⁹ = 0.6 seconds
Time_B = IC × CPI_B / f_B = 10⁹ × 2.0 / 3×10⁹ = 0.667 seconds

Processor A is faster despite lower clock rate!

Lesson: Clock rate alone doesn’t determine performance. CPI matters equally.

MIPS (Million Instructions Per Second)

MIPS = IC / (Time × 10⁶) = Clock Rate / (CPI × 10⁶)

Problem: MIPS doesn’t account for instruction complexity. A CISC processor with fewer instructions may have higher MIPS but lower performance.

MFLOPS (Million FLOPS)

MFLOPS = FP Operations / (Time × 10⁶)

Better for floating-point workloads, but doesn’t capture integer performance.

CPI and Memory Effects

Cache misses significantly affect CPI:

Effective CPI = Base CPI + Memory Stall Cycles

Memory Stalls = Memory Accesses per Instruction × Miss Rate × Miss Penalty

Example:

• Base CPI = 1.0
• 1.5 memory accesses per instruction
• 5% L1 miss rate, 10 cycle L2 penalty

Effective CPI = 1.0 + 1.5 × 0.05 × 10 = 1.75

With 2% L1 miss rate:

Effective CPI = 1.0 + 1.5 × 0.02 × 10 = 1.30

34% CPI improvement just by reducing L1 miss rate from 5% to 2%!

Multi-Cycle Instructions

Different instructions take different numbers of cycles:

CPI = Σ (Fraction_i × Cycles_i)

Performance Comparison

Processor Comparison

Performance_A / Performance_B = Time_B / Time_A

= (IC_B × CPI_B × T_B) / (IC_A × CPI_A × T_A)

If IC_A = IC_B (same program):
= (CPI_B × T_B) / (CPI_A × T_A)
= (CPI_B / CPI_A) × (f_A / f_B)

Example

Processor A: 2 GHz, CPI = 1.5 Processor B: 4 GHz, CPI = 2.5

Speedup = (CPI_B / CPI_A) × (f_A / f_B)
= (2.5 / 1.5) × (2 / 4)
= 1.667 × 0.5
= 0.833

Processor A is 1/0.833 = 1.2× faster despite half the clock rate!

Interview Questions

1. Q: Write the CPU performance equation and explain each component. A: CPU Time = IC × CPI × T = IC × CPI / f. IC = instruction count (affected by ISA, compiler). CPI = cycles per instruction (affected by microarchitecture, cache). T = clock period (affected by process technology). f = clock rate = 1/T.

2. Q: Two processors run the same program. A: 3 GHz, CPI 2.0. B: 2 GHz, CPI 1.2. Which is faster? A: Time_A = IC × 2.0 / 3G. Time_B = IC × 1.2 / 2G. Ratio = (2.0/3) / (1.2/2) = 0.667 / 0.6 = 1.11. Processor B is 1.11× faster despite lower clock rate.

3. Q: How do cache misses affect CPI? A: Effective CPI = Base CPI + Miss Rate × Miss Penalty × Memory Accesses per Instruction. A 5% miss rate with 10 cycle penalty and 1.5 accesses/instruction adds 0.75 cycles to CPI.

4. Q: Why is MIPS a poor performance metric? A: MIPS doesn’t account for instruction complexity. A CISC processor executes fewer but more complex instructions, giving high MIPS but potentially lower actual performance. MIPS also varies with the same processor on different programs.

5. Q: What are the three ways to improve CPU performance? A: (1) Reduce instruction count (better algorithms, compiler). (2) Reduce CPI (better microarchitecture, caches, branch prediction). (3) Increase clock rate (smaller transistors, better process).

Common Mistakes

• ❌ Assuming clock rate alone determines performance
• ❌ Not accounting for CPI differences between processors
• ❌ Forting that IC depends on the ISA (RISC vs CISC)
• ❌ Not considering memory stall cycles in CPI
• ❌ Using MIPS as a performance comparison metric

Summary

CPU Time = IC × CPI / Clock Rate. Performance depends on all three factors, not just clock rate. CPI is heavily affected by cache misses and branch mispredictions. Optimization can target any component, but reducing CPI (through cache and pipeline improvements) often provides the biggest gains.

Cross-References

• Amdahl’s Law — Parallel speedup limits
• Cache Performance — CPI impact of cache misses
• Benchmarking — Measuring these metrics
• Performance Counters — Hardware measurement

Cross References

• Amdahl’s Law
• Benchmarking
• Cache Performance